Nowadays highly integrated semiconductor components for wireless communication include digital as well as analog circuits for data and signal processing on a chip. Digital signal-processing circuits are implemented by means of dedicated datapath-oriented circuits. Alternatively, implementation with a DSP (digital signal processor) is possible. A system with datapath architecture typically has complex circuit blocks which execute expensive and complicated arithmetic or trigonometric operations. A 5 GHz modem for wireless operation in an LAN (local area network) in accordance with the Standard IEEE 802.11a includes for example an FFT/IFFT (fast Fourier transform/inverse FFT) processor, a Viterbi decoder, a CORDIC processor and cross- and auto-correlators. The communication between those blocks is effected at high data rates. In that case periods of long inactivity frequently follow time portions with a high data throughput.
A serious technical problem in modern ASICs (application specific integrated circuits) is synchronisation of the different functional blocks which are integrated on a chip. The use of a global time clock for all functional blocks is to be embodied in the design only at a high level of complication and expenditure. In addition a synchronous global time clock produces increased electromagnetic interference (EMI). That causes difficulties in terms of integrating analog and digital circuits on a chip.
To resolve the above-indicated problems, in recent times so-called globally asynchronous, locally synchronous (GALS) circuit architectures have been proposed. Synchronously operating circuits trigger all storage operations in accordance with a common time raster which is defined by the status of a global signal. That signal is identified as the clock. Usually the rising edge of the clock signal is used for triggering storage operations. The disadvantage of synchronously operating circuits is that the basic assumption that the clock signal is available to all parts of the circuitry at the same moment in time—that is to say synchronously—is not correct in reality. That is governed by the signal propagation time.
Asynchronous circuits dispense with a time raster with discrete time steps. The function of asynchronous circuits is based on the occurrence of events. The instantaneous condition of the circuit is determined completely by the polarity of signal changes and the sequence thereof.
GALS circuits have circuit blocks which operate internally synchronously. Those locally synchronous circuit blocks communicate with each other asynchronously, that is to say by means of a handshake protocol. There is therefore no need for the individual, locally synchronised circuit blocks also to be globally synchronised with each other. As long as each individual locally synchronous block follows the handshake protocol, those circuit blocks can be combined together in any manner.
A GALS architecture is distinguished by a modular structure which permits a high level of flexibility in the circuit design. For, as the interface in relation to any locally synchronous circuit module is asynchronous, any synchronous circuits can be integrated with each other. Any locally synchronous circuit block can have a time raster with an individual clock signal frequency.
For conversion of the asynchronous communication between the locally synchronous circuit blocks, they each have a respective asynchronous wrapping circuit which is also referred to as an ‘asynchronous wrapper’. An asynchronous wrapper has input and output ports as well as a local clock signal generator. Each port of the wrapper, that is to say each input and each output, has an associated port control which is responsible for conversion of the handshake protocol. The port and the control together form an input unit and an output unit respectively.
The clock signal generator of an asynchronous wrapper is adapted to produce the clock signal at a signal frequency which is tuneable in a given frequency range. An important feature of clock signal generators for asynchronous wrappers is that the production of the clock signal can be interrupted (it is pausable).
The publication by David S Bormann, Peter Y K Cheoung, Asynchronous Wrapper for Heterogeneous Systems, In Proc International Conf Computer Design (ICCD), October 1997, pages 307 through 314 discloses an asynchronous wrapper with an input unit, an output unit and a clock signal generator. At the same time that article describes a method of clock control of an internally synchronous circuit block of an integrated circuit by means of an asynchronous wrapper. The input unit or the output unit produce and send a stretch signal to the clock signal generator when a request signal of an adjacent preceding circuit block was received at the input or a request signal was sent at the output to an adjacent subsequent circuit block. The stretch signal is present at a control input of the clock signal generator until a handshake has taken place for data exchange with an adjacent circuit. As long as the stretch signal is present the delivery of the next clock signal from the clock signal generator to the synchronous circuit block is delayed. In that way circuit blocks can be individually internally synchronously clock controlled and at the same time exchange data asynchronously with circuit blocks in the environment.
A disadvantage is that this asynchronous wrapper is designed for uses which are not specified in greater detail and it is therefore not suited to circuit environments which are predetermined in an individual case. That applies in particular in regard to power consumption which is required for a GALS block. Mechanisms for reducing the power consumption can only be implemented with difficulty, with the known asynchronous wrappers.